1. Field of the Invention
The present invention relates to semiconductor structures and, more particularly, to a semiconductor structure and a method of forming the semiconductor structure that provides either two individual resistors that are vertically isolated from each other, or a metal-insulator-metal (MIM) capacitor.
2. Description of the Related Art
A semiconductor resistor is a well-known structure that is commonly implemented as a strip of conducting semiconductor material. As with conventionally-formed discrete resistors, semiconductors resistors provide a predefined resistance to the flow of current through the semiconductor resistor.
A semiconductor capacitor is also a well-known structure that includes two conductive plates that are separated by a dielectric material. As with conventionally-formed discrete capacitors, semiconductor capacitors store energy in an electric field that exists across the two plates when a potential difference exists across the two plates.
Semiconductor resistors and capacitors are frequently implemented in the metal interconnect structure of an integrated circuit. One of the drawbacks of forming semiconductor resistors and capacitors in the metal interconnect structure is that it often takes a number of additional masking steps to form these devices, e.g., three or more separate masking steps to form a semiconductor resistor, and one or more separate masking steps to form a semiconductor capacitor. Thus, four or more additional masking steps can be required to include both resistors and capacitors in the metal interconnect structure.
In addition, when one of the plates of the capacitor is formed at the same time that a layer of metal traces is formed in the metal interconnect structure, the breakdown of the dielectric can be significantly reduced due to the large grain sizes of the metal used to form the metal traces, i.e., the metal used to form the metal traces is relatively rough and peaks in the rough surface reduce the distance between the plates.
Thus, there is a need for a method of forming semiconductor resistors and capacitors in the metal interconnect structure that requires fewer masking steps, and provides more uniform capacitance values.